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  <section id="vek280-dpucv2dx8g-reference-design">
<h1>VEK280 DPUCV2DX8G Reference Design<a class="headerlink" href="#vek280-dpucv2dx8g-reference-design" title="Permalink to this heading">¶</a></h1>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>Until the release of Versal™ AI Edge production speed files (currently targeted with release of Vivado 2023.2.1), PDI generation for Versal AI Edge will require an early enablement license that can be requested via the Versal AI Edge Errata Secure Site.  Also, the reference design archive does include a pre-compiled AIE object <code class="docutils literal notranslate"><span class="pre">libadf.a</span></code> for this specific DPU configuration, however, if the user wishes to reconfigure and recompile the DPUCV2DX8G, access to an AIE-ML Compiler early enablement license is required and can be obtained from the AIE Compiler Early Access Lounge.  Finally, the user will also want to have access to documentation such as the VEK280 schematics, user guide and BSPs which are provided in the VEK280 Early Access Lounge.  Please contact your local AMD sales or FAE contact to request access.</p>
</div>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>This design is based on the B01 version of the VEK280 evaluation board. It can also be leveraged with the A01 version of the board with specific limitations that are outlined below.</p>
</div>
<p>The reference design associated with this document <a class="reference external" href="https://www.xilinx.com/bin/public/openDownload?filename=DPUCV2DX8G_VAI_v3.5.tar.gz">is found
here</a>.</p>
<section id="table-of-contents">
<h2>Table of Contents<a class="headerlink" href="#table-of-contents" title="Permalink to this heading">¶</a></h2>
<ul class="simple">
<li><p><a class="reference external" href="#1-revision-history">1 Revision History</a></p></li>
<li><p><a class="reference external" href="#2-overview">2 Overview</a></p></li>
<li><p><a class="reference external" href="#3-software-tools-and-system-requirements">3 Software Tools and System
Requirements</a></p>
<ul>
<li><p><a class="reference external" href="#31-hardware">3.1 Hardware</a></p></li>
<li><p><a class="reference external" href="#32-software">3.2 Software</a></p></li>
</ul>
</li>
<li><p><a class="reference external" href="#4-design-files">4 Design Files</a></p>
<ul>
<li><p><a class="reference external" href="#41-design-components">4.1 Design Components</a></p></li>
</ul>
</li>
<li><p><a class="reference external" href="#5-tutorials">5 Tutorials</a></p>
<ul>
<li><p><a class="reference external" href="#51-board-setup">5.1 Board Setup</a></p></li>
<li><p><a class="reference external" href="#52-build-and-run-the-reference-design">5.2 Build and Run The Reference
Design</a></p>
<ul>
<li><p><a class="reference external" href="#521-build-the-dpu">5.2.1 Build the DPU</a></p></li>
<li><p><a class="reference external" href="#522-get-json-file">5.2.2 Get Json File</a></p></li>
<li><p><a class="reference external" href="#523-run-resnet50-example">5.2.3 Run ResNet50 Example</a></p></li>
</ul>
</li>
<li><p><a class="reference external" href="#53-change-the-configuration">5.3 Change the Configuration</a></p></li>
</ul>
</li>
<li><p><a class="reference external" href="#6-instructions-for-changing-the-platform">6 Instructions for Changing the
Platform</a></p>
<ul>
<li><p><a class="reference external" href="#61-dpucv2dx8g-ports">6.1 DPUCV2DX8G Ports</a></p></li>
<li><p><a class="reference external" href="#62-changing-the-platform">6.2 Changing the Platform</a></p></li>
</ul>
</li>
<li><p><a class="reference external" href="#7-instructions-for-adding-other-kernels">7 Instructions for Adding Other
Kernels</a></p>
<ul>
<li><p><a class="reference external" href="#71-rtl-kernel">7.1 RTL Kernel</a></p></li>
</ul>
</li>
<li><p><a class="reference external" href="#8-known-issues">8 Known Issues</a></p></li>
</ul>
</section>
<section id="revision-history">
<h2>1 Revision History<a class="headerlink" href="#revision-history" title="Permalink to this heading">¶</a></h2>
<p>Vitis AI 3.5 change log: - Update platform to B01 board with ES silicon,
and support Vitis 2023.1. - Support multi-batch setting</p>
<p>VitisAI 3.0 change log: - Initial early access version</p>
</section>
<hr class="docutils" />
<section id="overview">
<h2>2 Overview<a class="headerlink" href="#overview" title="Permalink to this heading">¶</a></h2>
<p>The Xilinx Versal Deep Learning Processing Unit (DPUCV2DX8G) is a
computation engine optimized for convolutional neural networks. It
includes a set of highly optimized instructions, and supports most
convolutional neural networks, such as VGG, ResNet, GoogLeNet, YOLO,
SSD, MobileNet, and others.</p>
<p>This tutorial contains information about:</p>
<ul>
<li><p>How to setup the VEK280 evaluation board.</p></li>
<li><p>How to build and run the DPUCV2DX8G reference design with VEK280
platform in Vitis environment.</p></li>
<li><p class="rubric" id="how-to-modify-the-platform">How to modify the platform.</p>
</li>
</ul>
</section>
<section id="software-tools-and-system-requirements">
<h2>3 Software Tools and System Requirements<a class="headerlink" href="#software-tools-and-system-requirements" title="Permalink to this heading">¶</a></h2>
<section id="hardware">
<h3>3.1 Hardware<a class="headerlink" href="#hardware" title="Permalink to this heading">¶</a></h3>
<p>Required:</p>
<ul class="simple">
<li><p>Revision B01 VEK280 evaluation board</p></li>
<li><p>USB type-C cable, connected to a PC for the terminal emulator</p></li>
<li><p>SD card</p></li>
</ul>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>If the target is an A01 board, a USB Ethernet Adapter is also required.</p>
</div>
</section>
<section id="software">
<h3>3.2 Software<a class="headerlink" href="#software" title="Permalink to this heading">¶</a></h3>
<p>Required:</p>
<ul class="simple">
<li><p>Vitis 2023.1</p></li>
<li><p>Python (version 2.7.5 or 3.6.8)</p></li>
<li><p>csh</p></li>
</ul>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p><code class="docutils literal notranslate"><span class="pre">bash</span></code> is used during the build but some <code class="docutils literal notranslate"><span class="pre">csh</span></code> scripts are used.</p>
</div>
</section>
</section>
<section id="design-files">
<h2>4 Design Files<a class="headerlink" href="#design-files" title="Permalink to this heading">¶</a></h2>
<section id="design-components">
<h3>4.1 Design Components<a class="headerlink" href="#design-components" title="Permalink to this heading">¶</a></h3>
<p>The top-level directory structure shows the the major design components.</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span>├── app
├── README.md
├── vek280_platform                        # VEK280 platform folder
│   ├── LICENSE
│   ├── Makefile
│   ├── hw
│   ├── sw
│   ├── platform
│   ├── platform.mk
│   └── README.md
├── vitis_prj                              # Vitis project folder
│   ├── Makefile
│   ├── scripts
│   ├── xv2dpu
│   └── xv2dpu_config.mk
└── xv2dpu_ip                              # DPUCV2DX8G IP folder
    ├── aie
    └── rtl
</pre></div>
</div>
</section>
</section>
<hr class="docutils" />
<section id="tutorials">
<h2>5 Tutorials<a class="headerlink" href="#tutorials" title="Permalink to this heading">¶</a></h2>
<section id="board-setup">
<h3>5.1 Board Setup<a class="headerlink" href="#board-setup" title="Permalink to this heading">¶</a></h3>
<p>Board jumper and switch settings:</p>
<p>Configure the Versal Boot Mode switch SW1 to boot from SD Card:</p>
<ul class="simple">
<li><p>SW1[1:4]- [ON,OFF,OFF,OFF].</p></li>
</ul>
</section>
<section id="build-and-run-the-reference-design">
<h3>5.2 Build and Run The Reference Design<a class="headerlink" href="#build-and-run-the-reference-design" title="Permalink to this heading">¶</a></h3>
<p>The following tutorials assume that the <cite>$TRD_HOME</cite> environment variable
is set as shown below.</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">%</span> <span class="n">export</span> <span class="n">TRD_HOME</span> <span class="o">=&lt;</span><span class="n">Vitis</span> <span class="n">AI</span> <span class="n">path</span><span class="o">&gt;/</span><span class="n">reference_design</span><span class="o">/</span><span class="n">DPUCV2DX8G</span><span class="o">-</span><span class="n">TRD</span>
</pre></div>
</div>
<p><strong>Step1:</strong> Build VEK280 platform</p>
<p>First, build the VEK280 platform in the folder <cite>$TRD_HOME/vek280_platform</cite>, more details refer to the instructions in <cite>$TRD_HOME/vek280_platform/README.md</cite>.</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">%</span> <span class="n">source</span> <span class="o">&lt;</span><span class="n">Vitis_install_path</span><span class="o">&gt;/</span><span class="n">Vitis</span><span class="o">/</span><span class="mf">2023.1</span><span class="o">/</span><span class="n">settings64</span><span class="o">.</span><span class="n">sh</span>

<span class="o">%</span> <span class="n">source</span> <span class="o">&lt;</span><span class="n">PetaLinux_install_path</span><span class="o">&gt;/</span><span class="n">settings</span><span class="o">.</span><span class="n">sh</span>

<span class="o">%</span> <span class="n">make</span> <span class="nb">all</span>
</pre></div>
</div>
<p><strong>Step2:</strong> Setup the environment for building the DPUCV2DX8G IP and
kernel</p>
<p>When platform is ready, set the Vitis environment variable as given below.</p>
<p>Open a linux terminal. Set the linux as Bash mode.</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">%</span> <span class="n">source</span> <span class="o">&lt;</span><span class="n">vitis</span> <span class="n">install</span> <span class="n">path</span><span class="o">&gt;/</span><span class="n">Vitis</span><span class="o">/</span><span class="mf">2023.1</span><span class="o">/</span><span class="n">settings64</span><span class="o">.</span><span class="n">sh</span>
</pre></div>
</div>
<section id="build-the-dpu">
<h4>5.2.1 Build the DPU<a class="headerlink" href="#build-the-dpu" title="Permalink to this heading">¶</a></h4>
<p>The default architecture of DPUCV2DX8G is C20B1 (<cite>CU_N=1</cite>,
<cite>BATCH_SingleCU=1</cite>, 16 AIE-ML cores for Convolution, 4 AIE-ML cores for
Non-Convolution), PL clock frequency is 300 MHz. This version of the
reference design only supports <cite>CU_N=1</cite>, but can support <cite>BATCH_SingleCU</cite> to
1~14. You can modify the file <cite>$TRD_HOME/vitis_prj/xv2dpu_config.mk</cite> to
change these parameters.</p>
<p>Execute the following command to build the project:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span>% cd $TRD_HOME/vitis_prj

% make all
</pre></div>
</div>
<p>Upon completion, you will find the generated SD card image here</p>
<p><cite>$TRD_HOME/vitis_prj/package_out/sd_card.img.gz</cite> and the implemented Vivado project here <cite>$TRD_HOME/vitis_prj/hw/binary_container_1/link/vivado/vpl/prj/prj.xpr</cite></p>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>You can execute <cite>make help</cite> to see more detailed information.</p>
</div>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>The implementation strategy may be changed by editing the file <cite>$TRD_HOME/vitis_prj/scripts/system.cfg</cite>. The default strategy is <code class="docutils literal notranslate"><span class="pre">prop=run.impl_1.strategy=Performance_ExploreWithRemap</span></code>.</p>
</div>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>If you are not modifying the configuration of the DPUCV2DX8G the compiled AIE Engine archive <cite>libadf.a</cite> can be reused. If you wish to skip compilation, comment out the last line of <cite>$TRD_HOME/vitis_prj/Makefile</cite>, which will save time when re-building the hardware design.</p>
</div>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="c1"># -@rm -rf aie</span>
</pre></div>
</div>
</section>
<section id="get-json-file">
<h4>5.2.2 Get Json File<a class="headerlink" href="#get-json-file" title="Permalink to this heading">¶</a></h4>
<p>The <cite>arch.json</cite> file is an important file required by Vitis AI. It works
together with the Vitis AI compiler to support model compilation with
various DPUCV2DX8G configurations. The <cite>arch.json</cite> file will be
generated by Vitis during the compilation of DPUCV2DX8G reference
design, it can be found in <cite>$TRD_HOME/vitis_prj/package_out/sd_card</cite>.</p>
<p>It can also be found in the following path:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span>$TRD_HOME/vitis_prj/hw/binary_container_1/link/vivado/vpl/prj/prj.gen/sources_1/bd/*/ip/*_DPUCV2DX8G_*/arch.json
</pre></div>
</div>
</section>
<section id="run-resnet50-example">
<h4>5.2.3 Run ResNet50 Example<a class="headerlink" href="#run-resnet50-example" title="Permalink to this heading">¶</a></h4>
<p>The reference design project has generated the matching model file in
<cite>$TRD_HOME/app</cite> path, pre-configured with default settings. If the
configuration of the DPUCV2DX8G is modified, the model needs to be
compiled with the new fingerprint file, <cite>arch.json</cite>.</p>
<p>In this section, we will execute this example.</p>
<p>Use the balenaEtcher tool to flash
<cite>$TRD_HOME/vitis_prj/package_out/sd_card.img.gz</cite> into SD card, insert the SD card with the image into the destination board and power up the board. After Linux boots, copy the folder <cite>$TRD_HOME/app</cite> in this reference design to the target folder <code class="docutils literal notranslate"><span class="pre">~/</span></code>, and run the following commands:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">%</span> <span class="n">cd</span> <span class="o">~/</span><span class="n">app</span><span class="o">/</span><span class="n">model</span><span class="o">/</span>

<span class="o">%</span> <span class="n">xdputil</span> <span class="n">benchmark</span> <span class="n">resnet50</span><span class="o">.</span><span class="n">xmodel</span> <span class="mi">1</span>
</pre></div>
</div>
<p>A typical output would appear as shown below:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">I1123</span> <span class="mi">04</span><span class="p">:</span><span class="mi">08</span><span class="p">:</span><span class="mf">22.475286</span>  <span class="mi">1127</span> <span class="n">test_dpu_runner_mt</span><span class="o">.</span><span class="n">cpp</span><span class="p">:</span><span class="mi">474</span><span class="p">]</span> <span class="n">shuffle</span> <span class="n">results</span> <span class="k">for</span> <span class="n">batch</span><span class="o">...</span>
<span class="n">I1123</span> <span class="mi">04</span><span class="p">:</span><span class="mi">08</span><span class="p">:</span><span class="mf">22.476413</span>  <span class="mi">1127</span> <span class="n">performance_test</span><span class="o">.</span><span class="n">hpp</span><span class="p">:</span><span class="mi">73</span><span class="p">]</span> <span class="mi">0</span><span class="o">%</span> <span class="o">...</span>
<span class="n">I1123</span> <span class="mi">04</span><span class="p">:</span><span class="mi">08</span><span class="p">:</span><span class="mf">28.476716</span>  <span class="mi">1127</span> <span class="n">performance_test</span><span class="o">.</span><span class="n">hpp</span><span class="p">:</span><span class="mi">76</span><span class="p">]</span> <span class="mi">10</span><span class="o">%</span> <span class="o">...</span>
<span class="o">.</span>
<span class="o">.</span>
<span class="o">.</span>
<span class="n">I1123</span> <span class="mi">04</span><span class="p">:</span><span class="mi">09</span><span class="p">:</span><span class="mf">22.478189</span>  <span class="mi">1127</span> <span class="n">performance_test</span><span class="o">.</span><span class="n">hpp</span><span class="p">:</span><span class="mi">76</span><span class="p">]</span> <span class="mi">100</span><span class="o">%</span> <span class="o">...</span>
<span class="n">I1123</span> <span class="mi">04</span><span class="p">:</span><span class="mi">09</span><span class="p">:</span><span class="mf">22.478253</span>  <span class="mi">1127</span> <span class="n">performance_test</span><span class="o">.</span><span class="n">hpp</span><span class="p">:</span><span class="mi">79</span><span class="p">]</span> <span class="n">stop</span> <span class="ow">and</span> <span class="n">waiting</span> <span class="k">for</span> <span class="nb">all</span> <span class="n">threads</span> <span class="n">terminated</span><span class="o">....</span>
<span class="n">I1123</span> <span class="mi">04</span><span class="p">:</span><span class="mi">09</span><span class="p">:</span><span class="mf">22.478495</span>  <span class="mi">1127</span> <span class="n">performance_test</span><span class="o">.</span><span class="n">hpp</span><span class="p">:</span><span class="mi">85</span><span class="p">]</span> <span class="n">thread</span><span class="o">-</span><span class="mi">0</span> <span class="n">processes</span> <span class="mi">20225</span> <span class="n">frames</span>
<span class="n">I1123</span> <span class="mi">04</span><span class="p">:</span><span class="mi">09</span><span class="p">:</span><span class="mf">22.478528</span>  <span class="mi">1127</span> <span class="n">performance_test</span><span class="o">.</span><span class="n">hpp</span><span class="p">:</span><span class="mi">93</span><span class="p">]</span> <span class="n">it</span> <span class="n">takes</span> <span class="mi">2299</span> <span class="n">us</span> <span class="k">for</span> <span class="n">shutdown</span>
<span class="n">I1123</span> <span class="mi">04</span><span class="p">:</span><span class="mi">09</span><span class="p">:</span><span class="mf">22.478543</span>  <span class="mi">1127</span> <span class="n">performance_test</span><span class="o">.</span><span class="n">hpp</span><span class="p">:</span><span class="mi">94</span><span class="p">]</span> <span class="n">FPS</span><span class="o">=</span> <span class="mf">337.061</span> <span class="n">number_of_frames</span><span class="o">=</span><span class="mi">20225</span> <span class="n">time</span><span class="o">=</span> <span class="mf">60.0039</span> <span class="n">seconds</span><span class="o">.</span>
<span class="n">I1123</span> <span class="mi">04</span><span class="p">:</span><span class="mi">09</span><span class="p">:</span><span class="mf">22.478579</span>  <span class="mi">1127</span> <span class="n">performance_test</span><span class="o">.</span><span class="n">hpp</span><span class="p">:</span><span class="mi">96</span><span class="p">]</span> <span class="n">BYEBYE</span>
</pre></div>
</div>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>For running other networks, refer to the <a class="reference external" href="https://github.com/Xilinx/Vitis-AI">Vitis AI Github</a> and <a class="reference external" href="https://docs.xilinx.com/r/en-US/ug1414-vitis-ai">Vitis AI User Guide</a>.</p>
</div>
</section>
</section>
<section id="change-the-configuration">
<h3>5.3 Change the Configuration<a class="headerlink" href="#change-the-configuration" title="Permalink to this heading">¶</a></h3>
<p>The DPUCV2DX8G IP provides some user-configurable parameters, refer to
the document <a class="reference external" href="https://docs.xilinx.com/r/en-US/pg425-dpu">PG425</a>.</p>
<p>In this reference design, user-configurable parameters are in the file <cite>$TRD_HOME/vitis_prj/xv2dpu_config.mk</cite>.</p>
<p>They are:</p>
<ul class="simple">
<li><p><code class="docutils literal notranslate"><span class="pre">CU_N</span></code> – Compute Unit (CU) number (only a value of 1 is supported in the current IP).</p></li>
<li><p><code class="docutils literal notranslate"><span class="pre">CPB_N</span></code> – number of AI Engine cores for Convolution per batch handler (only a value of 16 is supported for this design).</p></li>
<li><p><code class="docutils literal notranslate"><span class="pre">BATCH_SingleCU</span></code> – number of batch engine integrated in DPUCV2DX8G IP for CU_N=1. Values supported are 1 through 14.</p></li>
</ul>
<p>After changing <cite>$TRD_HOME/vitis_prj/xv2dpu_config.mk</cite>, execute <code class="docutils literal notranslate"><span class="pre">make</span> <span class="pre">all</span></code> to build the design.</p>
</section>
</section>
<hr class="docutils" />
<section id="instructions-for-changing-the-platform">
<h2>6 Instructions for Changing the Platform<a class="headerlink" href="#instructions-for-changing-the-platform" title="Permalink to this heading">¶</a></h2>
<section id="dpucv2dx8g-ports">
<h3>6.1 DPUCV2DX8G Ports<a class="headerlink" href="#dpucv2dx8g-ports" title="Permalink to this heading">¶</a></h3>
<p>The DPUCV2DX8G ports are listed as below.</p>
<table class="docutils align-default">
<thead>
<tr class="row-odd"><th class="head"><p>Ports</p></th>
<th class="head"><p>Descriptions</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>m*_&lt;wgt|img|instr&gt;_axi</p></td>
<td><p>Master AXI
interfaces,
connected with NOC
to access DDR
(cips_noc in this
reference design
platform)</p></td>
</tr>
<tr class="row-odd"><td><p>m*_&lt;data|ctrl&gt;_axis</p></td>
<td><p>Master AXI-stream
interface,
connected with AI
Engine
(ai_engine_0).</p></td>
</tr>
<tr class="row-even"><td><p>s*_&lt;data|done&gt;_axis</p></td>
<td><p>Slave AXI-stream
interface,
connected with AI
Engine
(ai_engine_0).</p></td>
</tr>
<tr class="row-odd"><td><p>m_axi_clk</p></td>
<td><p>Input clock used
for DPUCV2DX8G
general logic, AXI
and AXI-stream
interface. Default
frequency is 300M
Hz in this
reference design.</p></td>
</tr>
<tr class="row-even"><td><p>m_axi_aresetn</p></td>
<td><p>Active-Low reset
for DPUCV2DX8G
general logic.</p></td>
</tr>
<tr class="row-odd"><td><p>s_axi_control</p></td>
<td><p>AXI lite interface
for controlling
DPUCV2DX8G
registers,
connected with CIPS
through
A
XI_Smartconnect_IP.</p></td>
</tr>
<tr class="row-even"><td><p>s_axi_aclk</p></td>
<td><p>Input clock for
S_AXI_CONTROL.
Default frequency
is 150M Hz in this
reference design.</p></td>
</tr>
<tr class="row-odd"><td><p>s_axi_aresetn</p></td>
<td><p>Active-Low reset
for S_AXI_CONTROL.</p></td>
</tr>
<tr class="row-even"><td><p>interrupt</p></td>
<td><p>Interrupt signal
generated by
DPUCV2DX8G.</p></td>
</tr>
</tbody>
</table>
<p>DPUCV2DX8G’s connection with AI Engine array and NOC are all defined in
the <cite>$TRD_HOME/vitis_prj/scripts/xv2dpu_aie_noc.cfg</cite> (generated by <cite>xv2dpu_aie_noc.py</cite>).</p>
<p>For the clock design, make sure that:</p>
<ul class="simple">
<li><p>s_axi_aclk for <cite>s_axi_control</cite> should use clock with lower frequency (e.g. 150MHz) to get better timing.</p></li>
<li><p><cite>AI Engine Core Frequency</cite> should be 4 times of DPUCV2DX8G’s <cite>m_axi_clk</cite>, or the maximum AI Engine frequency. In this reference, it is 1250MHz (the maximum AI Engine frequency of XCVE2802-2MP device on the VEK280 board). The value of <cite>AI Engine Core Frequency</cite> can be set in the platform design files or <cite>vitis_prj/scripts/postlink.tcl</cite>.</p></li>
</ul>
</section>
<section id="changing-the-platform">
<h3>6.2 Changing the Platform<a class="headerlink" href="#changing-the-platform" title="Permalink to this heading">¶</a></h3>
<p>Changing platform needs to modify 1 files: <cite>vitis_prj/Makefile</cite>.</p>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>This target platform is based on ES device.</p>
</div>
<ol class="arabic simple">
<li><p><cite>vitis_prj/Makefile</cite>:</p></li>
</ol>
<ul class="simple">
<li><p>Change the path of <cite>xpfm</cite> file for the varibale <cite>PLATFORM</cite></p></li>
</ul>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">PLATFORM</span>           <span class="o">=</span> <span class="o">*/*.</span><span class="n">xpfm</span>
</pre></div>
</div>
<ul class="simple">
<li><p>Change the path of <cite>rootfs.exts</cite> and <cite>Image</cite> in the package section
(at the bottom of Makefile)</p></li>
</ul>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">--</span><span class="n">package</span><span class="o">.</span><span class="n">rootfs</span>     <span class="o">*/</span><span class="n">rootfs</span><span class="o">.</span><span class="n">ext4</span> \
<span class="o">--</span><span class="n">package</span><span class="o">.</span><span class="n">sd_file</span>    <span class="o">*/</span><span class="n">Image</span> \
</pre></div>
</div>
</section>
</section>
<hr class="docutils" />
<section id="instructions-for-adding-other-kernels">
<h2>7 Instructions for Adding Other Kernels<a class="headerlink" href="#instructions-for-adding-other-kernels" title="Permalink to this heading">¶</a></h2>
<p>Vitis kernels developed for Versal devices, could be RTL kernel (only
use PL resouces), AIE kernel (only uses AI Engine tiles), or kernel
including both PL and AIE. The basic instructions for adding other
kernels in this reference design are shown below.</p>
<section id="rtl-kernel">
<h3>7.1 RTL Kernel<a class="headerlink" href="#rtl-kernel" title="Permalink to this heading">¶</a></h3>
<p>Package the RTL kernel as XO file. Then modify 2 files:
<cite>vitis_prj/Makefile</cite>, and <cite>vitis_prj/scripts/xv2dpu_aie_noc.py</cite>,</p>
<ol class="arabic simple">
<li><p><cite>vitis_prj/Makefile</cite>:</p></li>
</ol>
<ul class="simple">
<li><p>Add the name of XO files in the parameters <cite>BINARY_CONTAINER_1_OBJS</cite>
by adding following command</p></li>
</ul>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">BINARY_CONTAINER_1_OBJS</span>   <span class="o">+=</span> <span class="n">xxx</span><span class="o">.</span><span class="n">xo</span>
</pre></div>
</div>
<ul class="simple">
<li><p>In the v++ linking command line, specify the clock frequency for the
clock soure of RTL kernel.</p></li>
</ul>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">--</span><span class="n">clock</span><span class="o">.</span><span class="n">freqHz</span> <span class="o">&lt;</span><span class="n">freqHz</span><span class="o">&gt;</span><span class="p">:</span><span class="o">&lt;</span><span class="n">kernelName</span><span class="o">.</span><span class="n">clk_name</span><span class="o">&gt;</span>
</pre></div>
</div>
<ol class="arabic simple" start="2">
<li><p><cite>vitis_prj/scripts/xvdpu_aie_noc.py</cite>:</p></li>
</ol>
<ul class="simple">
<li><p>Create instance for the RTL kernel, and map kernel ports to memory
(NOC)</p></li>
</ul>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">result</span> <span class="o">+=</span> <span class="s2">&quot;nk=&lt;kernel name&gt;:&lt;number&gt;:&lt;cu_name&gt;.&lt;cu_name&gt;...</span><span class="se">\n</span><span class="s2">&quot;</span>
</pre></div>
</div>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>For support with adding AI Engine kernel or RTL + AI Engine kernels to this design, please reach out to us for support.</p>
</div>
</section>
</section>
<section id="known-issues">
<h2>8 Known Issues<a class="headerlink" href="#known-issues" title="Permalink to this heading">¶</a></h2>
<ol class="arabic simple">
<li><p>This reference design has updated to support rev-B ES vek280 board,
if you want to use it on rev-A board, Ethernet will not work, however
you can use a USB Ethernet Adapter to workaround this issue.</p></li>
<li><p>This version of the reference design supports only a subset of the
Vitis AI Model Zoo models.</p></li>
<li><p>The app/model/resnet50.xmodel only support the default arch
setting(BATCH_SingleCU=1). To enable alternative batch settings, it
is necessary to compile the corresponding xmodel with a new arch.json
file.</p></li>
<li><p>It is suggested to add the following line to your tcl scripts
<cite>$HOME/.Xilinx/Vivado/Vivado_init.tcl</cite>. For details about
<cite>Vivado_init.tcl</cite>, please refer to the link page
<cite>https://docs.xilinx.com/r/en-US/ug894-vivado-tcl-scripting/Initializing-Tcl-Scripts</cite>.
This setting can help to optimize the ddr r/w performance by
preplacing the NoC netlist.</p></li>
</ol>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">set_param</span> <span class="n">place</span><span class="o">.</span><span class="n">preplaceNOC</span> <span class="n">true</span>
</pre></div>
</div>
<ol class="arabic simple" start="5">
<li><p>If your OS is Ubuntu, during AIE compilation step, you may get the error
like “[AIE ERROR] XAieSim_GetStackRange():522: Invalid Map file, 2: No
such file or directory”, the reason should be that your Ubuntu does not
install the “rename” function, you can install it manually.</p></li>
</ol>
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